Testbench reset

`timescale 1 ns/1 ps
`include “top.v”
module counter_tb;
reg clk, reset, enable;
wire [3:0] count;

counter U0 (
.clk (clk),
.reset (reset),
.enable (enable),
.count (count)
);

task reset_task;
input[15:0]reset_time;
begin
reset=0;
#reset_time;
reset=1;
end
endtask

//main cycle
initial begin
clk = 0;
enable = 0;
reset_task(100);
enable = 1;
end

parameter PERIOD = 20; // 20ns

always begin
#(PERIOD/2) clk = 0;
#(PERIOD/2) clk = 1;
end

initial begin
$dumpfile (“counter.vcd”);
$dumpvars;
end

initial begin
$display(“\t\ttime,\tclk,\treset,\tenable,\tcount”);
$monitor(“‰d,\t‰b,\t‰b,\t‰b,\t‰d”,$time, clk,reset,enable,count);
end

initial
#1000 $finish;

//Rest of testbench code after this line

endmodule