Run_test.do

transcript on
if ![file isdirectory verilog_libs] {
file mkdir verilog_libs
}

vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {c:/altera/16.0/quartus/eda/sim_lib/altera_primitives.v}

vlib verilog_libs/lpm_ver
vmap lpm_ver ./verilog_libs/lpm_ver
vlog -vlog01compat -work lpm_ver {c:/altera/16.0/quartus/eda/sim_lib/220model.v}

vlib verilog_libs/sgate_ver
vmap sgate_ver ./verilog_libs/sgate_ver
vlog -vlog01compat -work sgate_ver {c:/altera/16.0/quartus/eda/sim_lib/sgate.v}

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {c:/altera/16.0/quartus/eda/sim_lib/altera_mf.v}

vlib verilog_libs/altera_lnsim_ver
vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
vlog -sv -work altera_lnsim_ver {c:/altera/16.0/quartus/eda/sim_lib/altera_lnsim.sv}

vlib verilog_libs/cycloneive_ver
vmap cycloneive_ver ./verilog_libs/cycloneive_ver
vlog -vlog01compat -work cycloneive_ver {c:/altera/16.0/quartus/eda/sim_lib/cycloneive_atoms.v}

if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/LED_module.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/SPI_module.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/Dut_def.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/SPI_phy.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/Top_module.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1 {D:/Project/Altera/TEST1/MSPI_agent.v}
vlog -vlog01compat -work work +incdir+D:/Project/Altera/TEST1/simulation/modelsim {D:/Project/Altera/TEST1/simulation/modelsim/Top_module.vt}

#vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=”+acc” test
vsim -novopt -t 1ps work.Top_module_vlg_tst

#add wave *
add wave -position insertpoint \
sim:/Top_module_vlg_tst/mspi/CLK \
sim:/Top_module_vlg_tst/mspi/MSCLK \
sim:/Top_module_vlg_tst/mspi/RST_N \
sim:/Top_module_vlg_tst/mspi/EN \
sim:/Top_module_vlg_tst/mspi/CS \
sim:/Top_module_vlg_tst/mspi/MISO \
sim:/Top_module_vlg_tst/mspi/MOSI \
sim:/Top_module_vlg_tst/mspi/SCLK \
sim:/Top_module_vlg_tst/mspi/IRQ \
sim:/Top_module_vlg_tst/mspi/TX_BUFFER \
sim:/Top_module_vlg_tst/mspi/TX_state
view structure
view signals
#run -all
restart -f
run 1us