常见数字IC设计or FPGA简单问题

1:什么是同步逻辑和异步逻辑? 同步逻辑是时钟之间有固定的因果关系。异步逻辑是各时钟之间没有固定的因果关系。 同步时序逻辑电路的特点:各触发器的时钟端全部连接在一起,并接在系统时钟端,只有当时钟脉冲到来时,电路的状态才能改变。改变后的状态将一直保持到下一个时钟脉冲的到来,此时无论外部输入 x 有无变化,状态表中的每个状态都是稳定的。    异步时序逻辑电路的特点:电路中除可以使用带时钟的触发器外,还可以使用不带时钟的触发器和延迟元件作为存储元件,电路中没有统一的时钟,电路状态的改变由外部输入的变化直接引起。

Testbench reset

`timescale 1 ns/1 ps `include “top.v” module counter_tb; reg clk, reset, enable; wire [3:0] count; counter U0 ( .clk (clk), .reset (reset), .enable (enable), .count (count) ); task reset_task; input[15:0]reset_time; begin reset=0; #reset_time; reset=1; end endtask //main cycle initial begin clk = 0; enable = 0; reset_task(100); enable = 1; …

Xilinx JTAG for Ubuntu 15.04

On 32-bit sudo apt-get install gitk git-gui libusb-dev build-essential libc6-dev fxload On 64-bit sudo apt-get install gitk git-gui libusb-dev build-essential libc6-dev-i386 fxload Download the driver source You should firstly change to the installation directory. You need (assuming default install path) to change directory to /opt/Xilinx. Then you will be required …

Ubuntu15.04 with ISE14.7 problem

Started : “Creating ChipScope Definition File”. Running inserter… Command Line: inserter -intstyle ise -mode initial -proj /home/ruanxi/Documents/X_Project/LP_Sensor_Project_FPGA/Source/tt.cdc -p xc6slx16 -output_dir _ngo -ise_project_dir /home/ruanxi/Documents/X_Project/LP_Sensor_Project_FPGA /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/inserter: 72: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/cs_common.sh: XIL_DIRS[0]=/opt/Xilinx/14.7/ISE_DS/ISE/: not found /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/inserter: 73: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/cs_common.sh: count++: not found /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/inserter: 152: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/cs_common.sh: Syntax error: Bad for loop variable ERROR: Unable to create CDC source …